It is well known that integrated circuits (also referred to as “chips”) are often coupled to a printed circuit board using a package substrate (also sometimes referred to herein as a “package”). In a typical flip type chip, the bottom of the chip includes a bump array having a plurality of solder bumps that are used to electrically connect and bond the chip to the package substrate.
FIG. 1A is a simplified top illustration of a portion of a typical prior art bump array 10P positioned on a prior art package substrate 12P, and FIG. 1B is a simplified cut-away view taken on line 1B-1B of FIG. 1A. The prior art bump array 10P includes a plurality of signal bumps 14P, a plurality of ground bumps 16P, and a plurality of power bumps 18P. Further, in this design, the package substrate 12P includes a plurality of signal traces 20P positioned in a signal layer that are electrically connected to the signal bumps 14P, a ground plane 24P that is electrically connected to the ground bumps 16P with ground vias 26P, and a power plane 28P that is electrically connected to the power bumps 18P with power vias 30P.
The prior art flip chip bump array 10P illustrated in FIGS. 1A and 1B includes two rows of signal bumps 14P, followed by a row of ground bumps 16P, and a row of power bumps 18P. This arrangement makes it possible to use (i) a common signal layer in the package substrate 12P for the individual signal traces 20P, (ii) a solid ground plane 24P in the package substrate 12P for connecting to the ground bumps 16P, and (iii) a solid power plane 28P in the package substrate 12P for routing the power bumps 18P.
Unfortunately, with this design, the signal traces 20P for the signal bumps 14P in the second row of signal bumps 14P include a necked down region 32P having a reduced trace width. This necked down region 32P creates a high impedance region for that section of the signal traces 20P. Moreover, with this design, the signal traces 20P are tightly coupled. This increases signal-to-signal crosstalk between the signal traces 20P.